Sigma-delta modulator and an output rate reduction method thereof

ABSTRACT

A sigma-delta modulator and an output rate reduction method are disclosed. The sigma-delta modulator comprises an integrator, an analog-to-digital converter, and a controller. An input signal is received by the integrator to generate an integrated signal. The integrated signal is then converted by the analog-to-digital converter into a digital modulation signal. The input signal is received by the controller to calculate an input signal power. The analog-to-digital converter can be controlled by the controller based on a predetermined power value and a sum of the input signal power and a total quantization error power. By the way mentioned above, the out rate of the sigma-delta modulator is reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a sigma-delta modulator, and moreparticularly, to a sigma-delta modulator and an output rate reductionmethod.

2. Description of the Prior Art

Efficiency of conventional class A or class B amplifiers is usually lessthan 60%, and thus large-sized thermal diffuser is necessarily disposed.Digital amplifiers are more generally utilized because digitalamplifiers amplify signals by switching techniques with efficiency up tomore than 90%. Therefore, the large-sized thermal diffuser is no longerneeded and the digital amplifier can be made very small.

The conventional digital amplifiers mostly use Pulse Width Modulation(PWM) with carrier signals. Therefore, the output spectrum of thedigital amplifier includes carrier frequencies and sidebands, and whichcause electromagnetic interference (EMI). To suppress EMI, PWM can bereplaced by a sigma-delta modulator as the output spectrum of thesigma-delta modulator is similar to white noise. However, the dataoutput rate of the sigma-delta modulator is higher than that of PWM, andwhich causes more switch loss in the digital amplifier.

SUMMARY OF THE INVENTION

To prevent the above mentioned problems, a sigma-delta modulator and anoutput rate reduction method is thus disclosed. The sigma-deltamodulator and the method can be utilized in a digital amplifier toreduce switch loss.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a sigma-delta modulator according thepresent invention.

FIG. 2 is a block diagram of a sigma-delta modulator according to afirst embodiment of the present invention.

FIG. 3 is a block diagram of a sigma-delta modulator according to asecond embodiment of the present invention.

FIG. 4 is a flow chart corresponding to FIG. 1.

FIG. 5 is a flow chart corresponding to the first embodiment in FIG. 2.

FIG. 6 is a flow chart corresponding to the second embodiment in FIG. 3.

DETAILED DESCRIPTION

The sigma-delta modulator and an output rate reduction method accordingto embodiments of the present invention will be described in detailbelow accompanied drawings.

Referring to FIG. 1, FIG. 1 is a block diagram of a sigma-deltamodulator according the present invention. The sigma-delta modulator 10includes an integrator 11, a first analog-to-digital converter (ADC) 12,and a controller 14. The integrator 11 receives an input signal 101 andgenerates an integrated signal 111 accordingly. The first ADC 12 iselectrically coupled to the integrator 11 and converts the integratedsignal 111 into a digital modulation signal 121 with feedback to theintegrator 11. The controller 14 is electrically coupled to the firstADC 12 to receive the input signal 101 for calculating an input signalpower 141, and the controller 14 controls the first ADC 12 according toa summation of the input signal power 141 and a total quantization errorpower 142, and a predetermined power value 144. When the summation isless than the predetermined power value 144, the controller 14 locks thefirst ADC 12 and sets the total quantization error power 142 for anaccumulated quantization error power 143 multiplied by a noise powergain, where the quantization error power can be represented by Δ²/12.The equation of the mentioned accumulation of the quantization errorpower 143 is presented below:Eq(i)=Eq(i−1)+Δ²/12.

When the summation is no less than the predetermined power value 144,the controller 14 unlocks the first ADC 12, the quantization error powerreturns to Δ²/12, and the total quantization error power 142 equalsΔ²/12 multiplied by the noise power gain. Please note that in thisembodiment, the predetermined power value 144 is the maximum outputsignal power of the first ADC 12, but the scope of the present inventionis not limited to this embodiment and the predetermined value can varywith the design.

If the first ADC 12 is locked, the digital modulation signal 121 will befixed by the first ADC 12, meaning that the digital modulation signal121 does not vary with the integrated signal 111. If the first ADC 12 isunlocked, the first ADC 12 will operate normally, meaning that thedigital modulation signal 121 varies with the integrated signal 111. Inaddition, the sigma-delta modulator 10 further includes a clock unit toprovides the controller 14 and the first ADC 12 with a clock signal.

The above mentioned first ADC 12 can be implemented with a bitquantizer, where the digital modulation signal 121 is a bit signal andthe input signal 101 is either an analog signal or a digital signal. Ifthe input signal 101 is an analog signal, the integrator 11 can beimplemented with an analog integrator and a sampler, the controller 14with a second ADC, a power look-up table, and state controller. If theinput signal 101 is a digital signal, the integrator 11 can beimplemented with a digital integrator, the controller 14 with a powercalculating unit and a state controller.

Referring to FIG. 2, FIG. 2 is a block diagram of a sigma-deltamodulator according to a first embodiment of the present invention. Thesigma-delta modulator 20 receives a digital signal. The sigma-deltamodulator 20 includes a digital integrator 21, a bit quantizer 22, apower calculating unit 24, and a state controller 25. The digitalintegrator 21 receives a digital input signal 201 and generates anintegrated signal 211. The bit quantizer 22 converts the integratedsignal 211 into a digital modulation signal 221 and has a feedback tothe digital integrator 21. The power calculating unit 24 receives thedigital input signal 201 and calculates a input signal power 241. Thestate controller 25 controls the bit quantizer 22 according to asummation of the input signal power 241 and a total quantization errorpower 242, and a predetermined power value 244. When the summation isless than the predetermined power value 244, the state controller 25locks the bit quantizer 22, meaning that the output of the bit quantizer22 has no transition, and the total quantization error power 242 equalsan accumulated quantization error power 243 multiplied by a noise powergain. On the other hand, when the summation is no less than thepredetermined power value 244, the state controller 25 unlocks the bitquantizer 22, meaning that the bit quantizer 22 operates normally. Then,the quantization error power 243 returns to Δ²/12 and the totalquantization error power 242 equals Δ²/12 multiplied by the noise powergain.

Referring to FIG. 3, FIG. 3 is a block diagram of a sigma-deltamodulator according to a second embodiment of the present invention. Thesigma-delta modulator 30 receives an analog signal. The sigma-deltamodulator 30 includes an analog integrator 31, a sampler 32, a bitquantizer 33, a digital-to-analog converter (DAC) 34, ananalog-to-digital converter 35, a power look-up unit 36, and a statecontroller 25. The analog integrator 31 receives an analog input signal301 and generates an analog integrated signal 311. The sampler 32samples the analog integrated signal 311 to generate a discrete timesignal 321. The bit quantizer 33 converts the discrete time signal 321into a digital modulation signal 331. The DAC 34 converts the digitalmodulation signal 331 into an analog feedback signal 341 to the analogintegrator 31. The ADC 35 receives the analog input signal 301 andconverts the analog input signal 301 into a digital signal 351. Thepower look-up unit 36 receives the digital signal 351 and generates ainput signal power 361 according to a look-up table 362. The statecontroller 37 controls the bit quantizer 33 according to a summation ofthe input signal power 361 and a total quantization error power 363, anda predetermined power value 365. When the summation is less than thepredetermined power value 365, the state controller 37 locks the bitquantizer 33. The total quantization error power 363 equals anaccumulated quantization error power 364 multiplied by a noise powergain. On the other hand, when the summation is no less than thepredetermined power value 365, the state controller 37 unlocks the bitquantizer 33. Then, the quantization error power 364 returns to Δ²/12.The state controller 37 sets the total quantization error power 363 forΔ²/12 multiplied by the noise power gain, and the predetermined powervalue 365 for the maximum output power of the sigma-delta modulator 30.The look-up table 362 stores the relationships between the digitalsignal 351 and its corresponding power. Please also note that in thisembodiment, the setting of the predetermined power value 365 is simplyan example, and the scope of the present invention is not limited tothis embodiment and the setting can vary with the design.

Referring to FIG. 4, FIG. 4 is a flow chart corresponding to FIG. 1. Thesigma-delta modulator 10 receives an input signal 101. In step S41, ainput signal power 141 is calculated and obtained according to the inputsignal 101. In step S42, a output signal power is obtained by summingthe input signal power 141 and a total quantization error power 142. Instep S43, the first ADC 12 is controlled according to the output signalpower and a predetermined power value 144.

When the above mentioned output signal power is less than thepredetermined power value 144, the first ADC 12 is locked, and the totalquantization error power 142 equals the accumulated quantization errorpower 143 multiplied by the noise power gain. On the other hand, whenthe above mentioned output signal power is no less than thepredetermined power value 144, the first ADC 12 is unlocked. Thequantization error power 143 returns to Δ²/12, and the totalquantization error power 142 equals Δ²/12 multiplied by the noise powergain. Please note that in this embodiment, the predetermined power value144 is the maximum output signal power of the first ADC 12, but thescope of the present invention is not limited to this embodiment and thepredetermined value can vary with the design. In addition, if the firstADC 12 is locked, the digital modulation signal 121 is fixed; if thefirst ADC 12 is unlocked, the first ADC 12 will operate normally.

Please note that the implementation of each device in the above flowchart has been well described in FIG. 1, and the scope of the presentinvention is not limited to the mentioned embodiments.

Referring to FIG. 5, FIG. 5 is a flow chart corresponding to the firstembodiment in FIG. 2. The sigma-delta modulator 20 receives a digitalinput signal 201. In step S51, a power calculating unit 24 is disposedand the power calculating unit 24 receives the digital input signal 201and calculates an input signal power 241. In step S52, a statecontroller 25 is disposed electrically coupled to the ADC, forcalculating a summation of the input signal power 241 and a totalquantization error power 242. In step S53, the state controller 25determines whether the summation is less than the maximum output signalpower of the bit quantizer 22. In step S54, if the summation is lessthan the maximum output signal power of the bit quantizer 22, the bitquantizer 22 is locked; the total quantization error power 242 equalsthe accumulated quantization error power 243 multiplied by the noisepower gain; back to step S51. In step S55, if the summation is no lessthan the maximum output signal power of the bit quantizer 22, the bitquantizer 22 is unlocked; the quantization error power 243 returns toΔ²/12, and the total quantization error power 242 equals Δ²/12multiplied by the noise power gain; back to step S51.

Referring to FIG. 6, FIG. 6 is a flow chart corresponding to the firstembodiment in FIG. 3. The sigma-delta modulator 30 receives an analoginput signal 301. In step S61, an ADC is disposed; the ADC receives theanalog input signal 301 and converts the analog input signal 301 into adigital signal. In step S62, a power look-up unit 36 is disposedelectrically coupled to the ADC, for calculating an input signal power361 according to a look-up table 362 and the digital signal. In stepS63, a state controller 37 is disposed electrically coupled to the ADC,for calculating a summation of the input signal power 361 and a totalquantization error power 363. In step S64, the state controller 37determines whether the summation is less than the maximum output powerof the bit quantizer 33. In step S65, if the summation is less than themaximum output power of the bit quantizer 33, the bit quantizer 33 islocked; the total quantization error power 363 equals an accumulatedquantization error power 364 multiplied by a noise power gain; back tostep S61. In step S66, if the summation is no less than the maximumoutput power of the bit quantizer 33, the bit quantizer 33 is unlocked;the quantization error power 364 returns to Δ²/12, and the totalquantization error power 363 equals Δ²/12 multiplied by the noise powergain; back to step S61.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A sigma-delta modulator, comprising: an integrator, for receiving aninput signal to generate an integrated signal; a first analog-to-digitalconverter, for converting the integrated signal into a digitalmodulation signal; and a controller, for receiving the input signal tocalculate an input signal power to control the first analog-to-digitalconverter according to a predetermined power value and a sum of theinput signal power and a total quantization error power.
 2. Thesigma-delta modulator of claim 1, wherein when the sum of the inputsignal power and the total quantization error power is less than thepredetermined power value, the first analog-to-digital converter islocked by the controller.
 3. The sigma-delta modulator of claim 2,wherein the total quantization error power is generated according to anaccumulated quantization error power multiplied by a noise power gain.4. The sigma-delta modulator of claim 1, wherein when the sum of theinput signal power and the total quantization error power is no lessthan the predetermined power value, the first analog-to-digitalconverter is unlocked by the controller.
 5. The sigma-delta modulator ofclaim 4, wherein the total quantization error power is generatedaccording to a quantization error power multiplied by a noise powergain.
 6. The sigma-delta modulator of claim 1, further comprising aclock unit, for providing a clock signal.
 7. The sigma-delta modulatorof claim 1, wherein the predetermined power value is the maximum outputsignal power of the first analog-to-digital converter.
 8. Thesigma-delta modulator of claim 1, wherein the first analog-to-digitalconverter is a bit quantizer.
 9. The sigma-delta modulator of claim 1,wherein the controller further comprises a second analog-to-digitalconverter, for converting the input signal into a digital signal. 10.The sigma-delta modulator of claim 9, wherein the controller furthercomprises a look-up table, for obtaining the input signal poweraccording to the digital signal.
 11. The sigma-delta modulator of claim1, wherein the controller further comprises a state controller forcontrolling the first analog-to-digital converter.
 12. The sigma-deltamodulator of claim 1, wherein the controller further comprises a powercalculating unit, for obtaining the input signal power.
 13. Thesigma-delta modulator of claim 1 is utilized in a digital amplifier. 14.A method for reducing an output rate utilized in a sigma-deltamodulator, comprising: receiving an input signal; obtaining an inputsignal power according to the input signal; summing the input signalpower and a total quantization error power to obtain an output signalpower; and controlling an analog-to-digital converter according to theoutput signal power and a predetermined power value.
 15. The method ofclaim 14, further comprising: locking the analog-to-digital converterwhen the output signal power is less than the predetermined power value.16. The method of claim 14, wherein the total quantization error poweris generated according to a multiplication of an accumulatedquantization error power and a noise power gain.
 17. The method of claim14, further comprising: unlocking the analog-to-digital converter whenthe output signal power is no less than the predetermined power value.18. The method of claim 17, wherein the total quantization error poweris generated according to a multiplication of a quantization error powerand a noise power gain.
 19. The method of claim 14, wherein thepredetermined power value is the maximum output signal power of theanalog-to-digital converter.
 20. The method of claim 14, wherein theanalog-to-digital converter is a bit quantizer.
 21. The method of claim14, further comprising: converting the input signal into a digitalsignal; and obtaining the input signal power according to the digitalsignal and a look-up table.